block diagram general description features CS5826 dual pixel lvds display interface (ldi) transmitter usa: 4020 moorpark avenue suite 115 san jose, ca, 95117 tel: 408-243-8388 fax: 408-243-3188 sales@myson.com.tw www.myson.com.tw rev.0.92 september 2002 page 1 of 19 myson century, inc. taiwan: no. 2, industry east rd. iii, science-based industrial park, hsin-chu, taiwan tel: 886-3-5784866 fax: 886-3-5784349 the CS5826 converts 48 bits (dual pixel 24-bit color) of cmos/ttl data into 8 lvds (low voltage differential signalling) data streams. control signals (vsync, hsync, de and two user-defined signals) are sent during blanking intervals. the CS5826 provides 3 operating modes: single- in-single-out, dual-in-dual-out and single-in-dual- out. in single-in-single-out and dual-in-dual-out modes, single pixel data can be clocked into CS5826 at a maximum rate of 112mhz. in single-in-dual-out mode, CS5826 supports a maximum clock rate of 224mhz. dc balancing on a cycle-to-cycle basis, is also provided to reduce isi (inter-symbol interference). with dc balancing, a low distortion eye-pattern is provided at the receiver end of the cable. complies with openldi specification for digital display interface. 30 to 112 (224)mhz clock support. supports svga through qxga panel resolutions. drives long, low cost cables. dc balance data transmission to reduce isi distortion. supports single and dual pixel gui interface rejects cycle-to-cycle jitter. 5v tolerant on data and control input pins. programmable data and control strobe select (rising or falling edge strobe) support for two additional user-defined control signals in dc balanced mode compatible with tia/eia lvds standard. 100-pin lqfp. data_dcbal data_dcbal data_dcbal data_dcbal data_dcbal data_dcbal data_dcbal data_dcbal clk_dcbal pll p2s p2s p2s p2s p2s p2s p2s p2s p2s clk 7xclk ref outbuf .com .com .com .com 4 .com u datasheet
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